1. Field
Exemplary embodiments of the present invention relate to a memory device, and more particularly, to a repair operation of the memory device.
2. Description of the Related Art
FIG. 1 is a diagram explaining a repair operation in a conventional memory device (for example, a DRAM).
A memory device may include a plurality of memory banks and one of the memory banks is shown in FIG. 1. Referring to FIG. 1, the memory device includes a memory array 110 which includes a plurality of memory cells, a row circuit 120 for activating a word line selected by a row address R_ADD, and a column circuit 130 for accessing (reading or writing) data DATA of a bit line selected by a column address C_ADD.
A row fuse circuit 140 stores a row address corresponding to a defective memory cell in the memory array 110, as a repair row address REPAIR_R_ADD. A row repair circuit 150 compares the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 and the row address R_ADD inputted from an exterior of the memory device. If the repair row address REPAIR_R_ADD and the row address R_ADD correspond to each other, the row repair circuit 150 controls the row circuit 120 to activate a redundancy word line instead of a word line designated by the row address R_ADD. That is to say, row (word line) corresponding to the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 is replaced with a redundancy row (word line).
In the drawing, the reference symbol TACT denotes an active command for commanding the activation of a word line, and the reference symbol IPRE denotes a precharge command for commanding the deactivation of an activated word line. The reference symbols IRIS and IT denote a read command and a write command, respectively.
In the conventional row fuse circuit 140, laser fuses are generally included and used. Laser fuses store high or low logic level of data depending on whether the laser fuses are cut or not. Although the laser fuses may be programmed in a wafer level of a memory device, it is not possible to program the laser fuses after a wafer is mounted in a package. Also, it is difficult to design the laser fuses in a below a certain size, due to a limitation in decreasing the pitch length thereof.
In order to alleviate such issues, a nonvolatile memory such as an E-fuse array circuit, a NAND flash memory, a NOR flash memory, an MRAM (magnetoresistive random access memory), an STT-MRAM (spin transfer torque magnetoresistive random access memory), an ReRAM (resistive random access memory) and a PC RAM (phase change random access memory) as disclosed in U.S. Pat. Nos. 6,940,751, 6,777,757, 6,667,902, 7,173,851 and 7269047 is included in a memory device, and repair information (repair addresses) is stored in the nonvolatile memory, for use.
FIG. 2 is a diagram showing the use of a nonvolatile memory circuit to store repair information in a memory device.
Referring to FIG. 2, the memory device includes a plurality of memory banks BK0 and BK1, registers 210_0 and 210_1 which are provided in the respective memory banks BK0 and BK1 to store repair information, and a nonvolatile memory circuit 201.
The nonvolatile memory circuit 201 is a substitution circuit for the row fuse circuit 140 shown in FIG. 1. Repair information, that is, repair addresses, corresponding to all the banks BK0 and BK1 is stored in the nonvolatile memory circuit 201. The nonvolatile memory circuit 201 includes regions REGION0 and REGION1. Repair information corresponding to the memory bank BK0 is stored in the region REGION0, and repair information corresponding to the memory bank BK1 is stored in the region REGION1. The nonvolatile memory circuit 201 may be any nonvolatile memo such as an E-fuse array circuit, a NAND flash memory, a NOR flash memory, an MRAM (magnetoresistive random access memory), an STT-MRM (spin transfer torque magnetoresistive random access memory), a ReRAM (resistive random access memory) and a PC RAM (phase change random access memory).
The registers 210_0 and 210_1 are provided in the respective memory banks BK0 and BK1 and store repair information of the respective memory banks BK0 and BK1. The register 210_0 stores to the repair information of the memory bank BK0, and the register 210_1 stores the repair information of the memory bank BK1. The registers 210_0 and 210_1 may include latch circuits, and may store the repair information only while power is supplied. The register 210_0 receives the repair information stored in the region REGION0 of the nonvolatile memory circuit 201, and the register 210_1 receives the repair information stored in the region REGION1 of the nonvolatile memory circuit 201.
The repair information stored in the nonvolatile memory circuit 201 is transmitted to and stored in the registers 210_0 and 210_1 to be used for a repair operation. Since the nonvolatile memory circuit 201 is configured in an array, a predetermined time is required to call the data stored in the nonvolatile memory circuit 201. Because the memory device cannot make an immediate call for the data stored in the nonvolatile memory circuit 201, it is impossible to perform a repair operation by directly using the data stored in the nonvolatile memory circuit 201. Therefore, a boot-up operation, in which the repair information stored in the nonvolatile memory circuit 201 is transmitted to and stored in the registers 210_0 and 210_1, is performed, and a repair operation is performed using the repair information stored in the registers 210_0 and 210_1, after the boot-up operation is performed.
In order to program (write) the repair information repair addresses) in the nonvolatile memory circuit 201, a test is to be to performed for the memory banks BK0 and BK1 and a repair address is to be detected as a result of the test. As the test for the memory banks BK0 and BK1, a parallel test (or a compression test) is generally used. The parallel test is performed such that the same data is written in a plurality of memory cells, data is read from the memory cells written with the data, and a determination of pass is made when all the same data is read from the memory cells and as a fail when even one different datum is read from the memory cells. For example, after the same data of ‘0’ is written in memory cells corresponding to a 100th row (word line) of the memory bank BK0 and then a read operation is performed, the 100th row of the memory bank BK0 may be determined to be a pass row when data of ‘0’ are read from the memory cells and to be a fail row when data of ‘1’ is read from even one of the memory cells.
While such a parallel (compression) test may be performed for one memory bank as in the above-described example, the parallel (compression) test may be performed simultaneously for at least two memory banks BK0 and BK1. For example, after the same data of ‘0’ is written in memory cells corresponding to 100th rows of the memory banks BK0 and BK1 and then a read operation is performed, the 100th rows of the memory banks BK0 and BK1 may be determined to be a pass row when data of ‘0’ are read from the memory cells and to be a fail row when data of ‘1’ is read from even one of the memory cells. In this case, when a fail row, that is, a defective row, is detected, it is impossible to know whether the fail row exists in the memory bank BK0, in the memory bank BK1 or in both the memory banks BK0 and BK1.
In the case where a parallel′ test is performed for one memory bank, if a fail row is detected, an address corresponding to the detected fail row may be programmed in a corresponding region of the regions REGION0 and REGION1 of the nonvolatile memory circuit 201. For example, if a 50th row is determined to be a fail row as a result of performing a parallel test for the memory bank BK1, a repair address corresponding to the 50th row may be programmed in the region REGION1 of the nonvolatile memory circuit 201. However, in the case where a parallel test is performed simultaneously for the two memory banks BK0 and BK1, if a fail row is detected, an address corresponding to the detected fail row may be programmed in both the regions REGION0 and REGION1 of the nonvolatile memory circuit 201. For example, if 30th rows are determined to be a fail row as a result of performing a parallel test for the memory banks BK0 and BK1, a program operation is to be performed twice in such a way as to program a repair address corresponding to the 30th row in the region REGION0 of the nonvolatile memory circuit 201, and program a repair address corresponding to the 30th row in the region REGION1 of the nonvolatile memory circuit 201.